Numerical control device



Feb; 17, 1970 .v. DI CAMILLO 3,495,775

NUMERICAL CONTROL DEVICE Filed Dec. 1, 1966 4 Sheets-Sheet 1 BLOCK x62? POSITION TAPE I a FEEDBACK READER l ENCODER TRANSDUCER I u AUX.

7 FUNC. ns 2| EQSE DRIVE MACHINE j CONTROL MECHANISM TOOL INVENTOR CARMINE V. DiCAMlLLO ATTORNEYS 4 Sheets-Sheet 4 N8- v com moz moz mo -8 Feb. 17, 1970 cyv. DI CAMILLO NUMERICAL CONTROL DEVICE Filed Deo.- 1, 1966' INVENTOR CARMINE 'V. Di'CAMILLO 6Q- ow moz moz mo 8 5 4 m NE woo 11. w om I832 lillliilik ATTORNEY United States Patent 3,495,775 NUMERICAL CONTROL DEVICE Carmine V. Di Camillo, Silver Spring, Md., assignor to Bowles Engineering Corporation, Silver Spring, Md., a corporation of Maryland Filed Dec. 1, 1966, Ser. No. 598,502 Int. Cl. G06d 1/100; G06m 1/00; -G06f 15/46 U.S. Cl. 235-201 22 Claims ABSTRACT OF THE DISCLOSURE In a servomechanism for controlling the speed of a variable speed drive mechanism connected to a tool, a logic network for comparing command and position signals indicative of the instantaneous difference between the command and position signals. All bits in each signal being assigned different decimal equivalent weights. A bit-by-bit comparison is made wherein the highest order bit inequality between the command and position signals determines the polarity of this difference and is a measure of approximate error. A correction means in said logic network inhibits the approximate magnitude indication and provides for a modified approximate magnitude indication in accordance with the weight of a lower weighted pair of bits of said signals.

The present invention relates to digital logic networks, and particularly to such networks as are employed in digital systems to produce a control signal representative of the difference between two digital signals. Although the invention is described below as employed in a specific servomechanism utilizing digital techniques, particularly a numerically-controlled machine tool, it is to be understood that such description is illustrative only, andthat the logic techniques disclosed herein are applicable to any system in which comparison of two numerical indicia is required.

Position-control systems, such as the type which may be used to automatically position machine tools, are wellknown. Such systems generally employ a device or devices for producing a command signal indicative of the actual tool position, and a comparator for producing an error signal indicative of the instantaneous difference between the command and position signals. The error signal is employed to control the speed of a variable speed drive mechanism, such as a motor, which in turn controls the position of the machine tool. As the machine tool approaches the command position, the error signal necessarily decreases, thereby decreasing the speed of the drive mechanism, until eventually the tool achieves the desired position.

The inherent advantages of digital techniques, specifically accuracy and stability, have long been recognized as particularly applicable to position-control systems, and in fact, have found widespread utilization in this field. Specifically, a digital command signal and a digital position signal, when compared in a digital comparison device, enable stable position control of the machine tool with a degree of accuracy not readily attainable with analog type systems. However, the accuracy and stability achieved by such techniques have been at the sacrifice of simplicity and low cost. For example, assume that it is desired to position a machine tool with an accuracy of one one-thousandth of an inch over a twenty-four inch workbed. If a pure binary code is employed, a binary number having fifteen bits is required to represent all of the twenty-four thousand discrete tool positions. Thus, a fifteen bit command signal must be compared with a fifteen bit position signal to produce a fifteen bit error signal which must then be converted to analog form in a fifteen stage digital-to-analog converter device to produce a signal appropriate to control the speed of the motor or drive mechanism. Generally, the comparison of the digital signals is accomplished by some binary subtraction technique wherein complex subtraction and borr0w" circuits are employed, the borrow circuits being necessary to prevent signal reversal when the subtrahend exceeds the minuend in any comparison stage. In addition to requiring a large amount of circuitry, the borrow function is also time consuming, since the borrow status in the lower order stages must be resolved before the state of the difference signal in higher order stages can be finally determined. To further complicate these digital comparison and digital-to-analog conversion operations, many systems, in order to facilitate communication between a human programmer and the digital machine, employ Binary Coded Decimal (BCD) signals as opposed to pure binary signals. The BCD code is arrived at by taking each digit (decade) of a decimal number and translating it individually into binary form. Since there are ten possible values for each decade, a minimum of four binary stages is necessary to represent each decade. Not only does this require more stages than the pure binary code, thereby requiring additional logic circuitry, but the very nature of the BCD code makes it necessary to modify the BCD words so that they may be appropriately compared.

The present invention, in order to simplify the aforesaid comparison and error signal generation operations, is predicated upon making certain approximations insofar as system operation is concerned, which when utilized do not result in any reduction in positioning accuracy. These approximations will be discussed in detail below.

In order to explain the underlying theory of operation of this invention, reference is made to a specific system having stipulated parameter characteristics. Such a system is merely intended to be illustrative and not limiting on the scope of applicability of the techniques described. It is assumed that a numerically-controlled machine tool positioning system employs BCD signals of five decades (5 X4 or 20 binary stages) for both the command signal, A, and the position signal, B. Let it be further assumed that each signal describes an absolute position; that is, a numerical position with respect to some arbitrary zero reference point, and that the command signal remains constant until the machine tool is positioned according to the command. From these conditions it is desirous to achieve a quick responding position control, having zero position overshoot, with a minimum amount of circuitry.

An examination of the requirements for the signal employed to control the speed of the tool positioning drive mechanism indicates that high speed positioning with zero overshoot can be readily achieved by using a multiple range speed drive wherein the speed of the drive mechanism decreases in discrete steps in accordance with predetermined ranges of decreasing distances of the machine tool from its commanded position. Suppose, for example, a maximum speed of 1200 inches per minute is dictated for large differences between command and position signals, that a small speed of inches per minute is dietated for a contiguous range of somewhat smaller signal differences, that a 12 inch per minute speed is dictated for the next range of smaller signal differences, etc. This scheme provides the rapid response described for large differences of signal while having overshoot characteristics about the same as in the continuously variable speed type of system. In addition, this scheme eliminates the necessity of converting the digital difference between the command and position signals into a continuous analog error signal, and thereby requires only a relatively few speed command logic circuits. The logic circuits provide predetermined range-defining stages of the digital difference signal and do not require a conversion circuit associated with each stage of the signal. More importantly, however, this scheme permits elimination of the rigors of direct binary subtraction in favor of a pseudo-subtraction technique which results in only an approximation of the actual error. This approximation of the error signal is permissible since only the range of differences between the command and position signal is important as opposed to the actual instantaneous error as in prior art devices. As will be evident from the description which follows, the pseudo-subtraction technique is accomplished utilizing logic circuits which are less expensive and less complex than those required for direct subtraction or for prior art short cuts attempting to avoid such direct subtraction.

Next let us examine the nature of BCD command and position signals. Table 1 below lists the decimal Weights assigned to each of the 20 binary stages (A through A in the BCD command signal word, and the weights assigned to each of the 20 binary stages (B through B in the BCD position signal word:

TABLE 1 Decimal values of non-Zero As and Bs It is to be noted that corresponding stages in the command signal A and the position signal B are assigned equal weights, and that these assigned weights increase with increasing stage number. Thus for either of signals A or B, if only stage 11 (A or B is in the binary one state, all other stages being in the binary zero state, the value of the respective signal is greater than when only state 10 (A or B is in the binary one state.

Next let us define the general stages A, and B of the A and B signals respectively by:

20 20 A=ZA,; 13:213..

If We consider the fact that the command signal A remains unchanged for each individual positioning cycle, we may then use the A signal as a reference when making the comparison between it and the varying position signal B. At this point let us examine the possibility of developing a signal comprising twenty independent stages defined as C =A -B for the respective stages of signals A and B. That is, a direct stage by stage comparison is to be made irrespective of borrowing techniques and other stage interconnections associated with direct binary subtraction. From the truth table of Table 2 below we see each C, stage may assume one of three states in a three level'code having a positive value for A B a negative value for B A and a zero value for A =B TABLE 2.-TRUTH TABLE the highest order non-zero C stage must always be of the same polarity as the polarity of the difference between signals A and B. This is true because C is defined as the difference between A and B and thus the highest order nonzero C corresponds to the highest order of A and B in which an inequality exists. Obviously, the highest order inequality between A and B determines the polarity of the difference between these signals.

Similarly, in addition to determining the polarity of the difference between A and B, the highest order nonzero C stage provides an approximate measure of the magnitude of the ditference between A and B. For example, if C is (i.e. A =1, B =0) and is the highest order non-zero C stage at a particular instant of time, if we use C as a measure of error magnitude, it is seen from Table 1 that the approximated error is +40.000 (A :40.000). However, just how close this approximated erro-r magnitude is to the actual error magnitude depends upon the conditions in the lower order C stages which immediately precede C To illustrate this more clearly, consider the following example:

EXAMPLE 1 Let:

(1 :0 (A =0 binary 00.000 decimal; [3 :0 binary,

00.000 decimal).

C =+(A =1 binary, 40.000 decimal; B =0 binary,

00.000 decimal).

C =(A =0 binary, 00.000 decimal; B =1 binary,

20.000 decimal).

C =-(A =0 binary, 00.000 decimal; B =1 binary,

10.000 decimal).

C through C =0, or (thereby providing a maximum variation of :09999).

The actual error is clearly:

But according to our approximation using the highest nonzero C stage as a measure of the error, our approximate error is +40.000. A scheme whereby +40.000 is used to approximate a range between +00.001 and +l9.999 is clearly inadequate because of the size of the range and because the approximation lies outside the range.

Thus it apears that a corrective factor must be included in the error signal approximation to account for those situations when one or more of the lower order C stages which immediately preceed the highest order non-zero C, stage are of a polarity different from the polarity of said highest order non-Zero stage. If we consider the above example, we notice that if C through C are zero or then C the lowest order stage of the unbroken sequence of C stages preceeding and having an opposite polarity from the polarity of the highest order non-zero stage (C provides a better approximate measure of the magnitude of the error signal (10.000). It would appear then that where the highest order non-zero C stage is immediately preceeded by one or more of a consecutive chain of lower order stages having opposite polarity, that the lowest order stage of said chain might better be used as a measure of the magnitude of the error signal. The follow ing examples illustrate this technique. To facilitate explanation, C is defined as the highest order non-zero C stage at any given instant of time.

Thus, C =C and therefore the polarity of the error signal is Since C is immediately preceeded by one stage (C of opposite polarity, that stage is used to determine the magnitude of the error. Thus,

The resulting approximated error is thus +20.000. Computing the actual error using Table 1, it is seen that Thereby yielding an actual error range of +10.001 to 39.999. The error of 20 obtained by use of stage B =20 is in the middle of the range.

Thus C =C and the polarity of the error signal must be Since C (C is immediately preceeded by three stages of opposite polarity (C C18, C the lowest order of these stages (C is used to determine error magnitude. Thus,

and the approximate error is -10.000.

Computing the actual error using Table 1, it is seen that C C must be between 09.999 and +07.999, thereby yielding an actual error range of 02.001 to -19.999 with acquired signal of 10 again lying in about the middle of the range.

From Examples 2 and 3 above, it is clear the corrective factor improves the accuracy of our approximation by first placing the approximated error within the actual error range, and second by keeping the approximation within one order of magnitude of the true error. For many purposes this is suiiiciently accurate, and as will be illustrated subsequently, implementation of this corrective factor is rather straight forward and does not require complex circuitry.

There exists another problem with the approximation however, which results from the fact that a BCD code is employed. The theory employed in the above discussion, and the conclusion resulting therefrom, are as applicable to pure binary code as to 2BCD code. However, a peculiarity of the BCD code provides an additional problem in the error approximation to which consideration must be given. Since in BCD, four binary stages are'employed to define each decade of an equivalent decimal number, each binary decade has a sixteen-bit capacity of which only ten bits are used. For example, only the numbers 0000 (decimal through 1001 (decimal 9) may appear in each four stage BCD decade. Thus the numbers in the following list can never appear in any decade:

1010 (decimal 10) 1011 (decimal 11) 1100 (decimal 12) 1101 (decimal 13) 1110 (decimal 14) 1111 (decimal 15) Instead, these decimal numbers appear in conjunction with the next higher four-stage binary decade such that:

0001 0000 represents decimal 10 0001 0001 represents decimal 11 0001 0010 represents decimal 12 0001 0011 represents decimal 13 0001 0100 represents decimal 14 0001 0101 represents decimal 15 It is this six-bit excess capacity in each decade which creates additional problems for the techniques thus far described. The problems may best be illustrated by a particular example:

(Note that C the lowest order stage in the second decade is the highest order non-zero C, stage, and that C the next lowest stage and the highest order stage in the first decade, has an opposite sign.) Following the approximations developed above, the approximate error is found as follows:

The polarity of the error is the polarity of C (C thus The magnitude of the error is determined by C since C (C is the only immediately preceding C stage of opposite sign to C (C Thus, C =B =00.008 and the approximate error is +00.008.

Computing the actual error, it is seen that C =+01.000 C =08.000 c,=00.000 or i00.001

and the actual error range is +00.001 to +00.003.

of Ai-l-l (in decade j) Weight of At' (in decade j-1) =2 (within a decade) The cause of this disparity in these relationships is the restriction against using the six counts in each four stage decade representative of counts 10 through 15 as discussed above. It is clear that since the highest order stage in each decade is weighted at decimal 8, the lowest order stage of the next higher decade would have to be weighted at decimal 16 in order to achieve the same 2:1 rates that exist between contiguous stages within a decade. However, since the very nature of the BCD code precludes such a weighting, the ratio disparity is unavoidable.

In order to correct this factor it is necessary to modify the previously described magnitude determination technique where stage Cmis of one polarity and one or more of stages C C C are of the opposite polarity, and one or more of said opposite polarity stage is the highest order stage of a decade. Specifically, it has been found that under such conditions, shifting from lowest order stage in one decade to the second lowest order stage of the next lower decade generally produces satisfactory results. This is true because of the nature of the BCD code whereby counts representing decimal 10 through 15 are prohibited to the four binary stages in a decade. Specifically, if the highest order stage in any decade is part of the chain of C C etc, which require a shifting of the magnitude-determinative stage from C to some lower order C stage, there is a definite restriction on the states of the second and third stages of that decade. If 0.; is indicating that A =0, B.,,=1, then C and C cannot possibly be because this would require either B or B to be binary 1 thereby making the decimal value of the decade B through B greater than 9. Since the BCD code precludes this situation, it is apparent that stages 2 and 3 of the decade cannot comprise an extension of the unbroken chain of stages Cm-l, (Em-2, etc., and therefore their effect on our approximation is not as great as the effect produced by stage 4 of the decade.

The effect of this modification to our approximation technique may best be illustrated by a specific example:

EXAMPLE 5 Suppose that C through C assume the following states: Decade 5:

C17=+ (decimal +10.000) Decade 4:

C .(decimal 08.000)

C (decimal 014000) Decade 3:

C (decimal 00.800)

C (decimal 00.0l0) Decade 1:

C (decimal 00.008)

C (decimal 00.001)

In accordance with all of the techniques discussed above, we first determine the polarity from C '=C17, and find it to be We must note that C (C and C (C are of opposite polarity, and further that C is the highest order stage of decade 4. Thus we shift to the second stage of decade 4, C and conditionally assign the value for IA I or [B from Table 1. However, since the very next lower stage, C is also of opposite polarity to C (C we shift thereto for a conditional measure of our approximate error. But it is noted that C is followed by still another opposite polarity stage, C and we must therefore go to that stage to provide a conditional error magnitude. However, stage C is the highest order stage of decade 3, and we must therefore shift further to stage C the second stage of decade 3. Once again it is noted that C is followed by two stages (C C having polarity opposite to that of C so we continue to shift in search of our magnitude determinative bit. Since C is the highest order stage in decade 2 we must shift to stage C which in turn is preceeded by stages C and C having opposite polarity to C C is the highest order stage of decade 1 so we must shift further to stage C and since that is preceeded by stage C which has an opposite polarity to that of C we must go to C as our magnitude determinative stage. Thus our error magnitude, approximated, is:

and our approximate error is +00u00l.

As a check, it is noted that our actual error turns out to be +00.001.

While the approximate error in Example 5 turned out to be identical with the actual error, this is not necessarily true for all situations. 'For example, since the modification disregards the polarity of the second and third stages in each decade when jumping stages due to an opposite polarity condition at the highest order stage of a decade, Example 5 would have yielded the same approximate magnitude even if C C14, C C C7, C C and C were all rather than 0. However, under these conditions our actual error would be +06.667. Obviously, 0.001 is a rather poor approximation of 6.667, and therefore a further modification is called for. Such further modification must clearly take into consideration the eifect stages 2 and 3 of each decade may have when these stages are jumped in accordance with the above-described technique. Specifically, we have seen that if stages 2 and/or 3 are of opposite polarity to stage 4, and stage 4 is part of a chain of C C etc. having opposite polarity to C stage 2 or 3 must not be jumped together. It has been found that satisfactory results are achieved when the appropriate jump is made to the third stage rather than the second stage for these conditions. This is best illustrated 'by reconsidering the example which illustrated the need for this last-described modification:

EXAMPLE 6 Suppose that C through C assume the following states:

Decade 5:

C (decimal 10.000) Decade 4:

C =(decimal 08.000)

C i=+ (decimal +O4.000)

C (decimal +02.000)

C =(decimal 0l.000) Decade 3:

C (decimal -00.800)

C =+(decimal +00.400)

C1o=+ (decimal C (decimal 00.100) Decade 2:

C (decimal 00.080)

C (decimal +00.040)

C (decimal +00.020)

C (decimal 00.0l0) Decade 1:

C (decimal 00.008)

C (decimal +O0.004)

C (decimal +00.002)

C (decimal :-00.00l)

In accordance with our newly modified techniques, we first determine the polarity of our error signal from C =C and find it to be We must note that C (C and C (C are of opposite polarity, and further that C is the highest order stage of decade 4. Rather than shift to stage C the second order stage of decade 4, we notice that at least one (in this case both) of stages C and C (stages 2 and 3 of decade 4) are of opposite polarity to C and therefore we shift to stage C (stage 3 of decade 4). Since the next lower stage, C is not of the same polarity as the polarity of C C etc. (in this case C alone), we do not shift any further and C is the stage which determines the magnitude of our approximate error. (Note that because of the restrictions outlined above for the BCD code, stage C could not possibly have the same polarity as C and thus shifting would always stop at stage 3 of each decade under the situation where either stage 3 or stage 2 of any decade is of opposite polarity to stage 4 of that decade). Our approximate error magnitude as determined by C is seen to be [04.000] from Table 1. Thus our approximate error is +04.000. As discussed above in conjunction with Example 5, the actual error here is +6.667, so that our approximation is reasonably close.

To best summarize the techniques discussed above, the following rules for approximating an error signal, defined as the difference between BCD signals A and B, are listed:

(1) The polarity of the error signal is the polarity of C the highest order non-zero C stage.

(2) If C is zero or of the same polarity as C the magnitude of the approximated error signal is l l=l ml where [CI is the absolute value of the approximated error signal and |A is the absolute value indicated for 15m520 in Table 1.

(3) If C is immediately preceded by one or more of an unbroken chain of n lower order stages C C C having opposite polarity to C and none of these It lower order stages are the highest order stages of a decade, then the magnitude of the approximated error signal is:

(4) Where, as in Rule 3 an unbroken chain of n lower order stages of opposite sign to C immediately precede C and where one of said lower order stages is the highest (fourth) order stage in a decade, and

(a) where neither the second or third order stage of that decade are of opposite polarity to said fourth stage, then the magnitude of the approximated error is determined by said second stage unless the first stage of said decade is of the same polarity as said fourth stage, under which condition the magnitude is determined by reverting to Rule 3 and considering said first stage as part of the original unbroken chain of C C etc.

(b) where either or both of the second and third stages in said decade are of opposite polarity to said fourth stage, said third stage determines the magnitude of the approximated error signal.

It should be pointed out that Rules 1, 2, and 3 apply to the pure binary code as well as BCD, and that Rules 4(a) and 4(b) apply to only BCD. In addition, the principles employed in determining these rules are not to be considered limited to the particular codes discussed, but rather are adaptable to other codes having particular distinguishing features. The limiting consideration in this regard is that the techniques apply only to codes in which the stages are assigned weights of increasing value for ascending stage members.

As will be evident from the embodiment described below, the above described technique provides a sufficiently accurate digital comparison for many applications and eliminates the need for the expensive and complex circuitry required for rigorous direct digital subtraction techniques.

It is therefore an object of the present invention to provide a novel logic network for comparing two digital signals.

It is a further object of this invention to provide a novel logic network for approximating the difference between two digital signals with sufficient accuracy for many applications and with less complex and expensive components than was heretofore possible.

It is a further object of this invention to provide a control device wherein the difference between a fixed and a variable digital signal is approximated and said approximated difference is employed to effect an appropriate control function.

It is yet another object of this invention to provide a novel logic network for producing an error signal in digital type servomechanisms.

It is still another object of this invention to provide a position control device wherein the difference between digital position and command signal is approximated as an error signal and utilized to position a device in accordance with the command signal.

It is still another object of this invention to provide a novel numerically-controlled machine tool mechanism wherein the difference between the tool position and a command signal is approximated to produce an error signal having plural discrete ranges for driving the machine tool at plural speeds as a function of the distance of the tool from the command position.

The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description of one specific embodiment thereof, especially when taken in conjunction with the accompanying drawings, wherein:

FIGURE 1 is a block diagram of a typical system in which the techniques of this invention may be employed;

FIGURE 2a is a block diagram representing a standard comparison unit employing the logic techniques of this invention;

FIGURE 2b is a schematic representation of the block diagram of FIGURE 2a;

FIGURE 3 is a schematic representation of one complete comparison stage of a logic network employing the techniques of this invention;

FIGURES 4a and 4b are schematic representations of eight complete stages of a logic network employing the techniques of this invention; and

FIGURE 5 is a schematic representation illustrating how the output signals from the network of FIGURE 4 are utilized.

It is to be understood that the embodiments of this invention can take the form of fluidic, electronic, photoelectric, magnetic or other similar circuitry and that the description below, though directed solely toward fluidic circuits, is done so for illustrative purposes only.

Referring now to FIGURE 1, a particular system employing the logic techniques of this invention is illustrated. It must again be stressed that the logic techniques of this invention are adaptable for use in any system employing a digital comparison, however, it is described herein for illustrative purposes as utilized in a numerically controlled machine tool positioning device. Tape reader control unit 11 provides a predetermined length of tape containing position command information for one positioning cycle to the block tape reader unit 13. The tape reader control may comprise a group of logic circuits and tape feeding mechanism, both of which are conventional and form no part of this invention. The reader control 11 also verifies that the command positions of the previous positioning cycle have been reached and that various machine tool operations have been performed. The block tape reader 13 reads the command information from the block of tape as received from the reader control. In addition to providing position command information during each positioning cycle, the tape additionally contains information to control auxilliary functions, such as directing machine tool operation, and the block tape reader unit 13 distributes commands appropriately to perform these functions. The position command information is transferred to comparison device 15 in parallel form as a 20-bit binary coded decimal (BCD) word. It is to be understood that three dimensional tool positioning may be accomplished by use of three distinct digital words, each representing a positional command along a different axis. For purposes of simplification, the operation described herein deals with only one dimensional operation and one digital command Word is supplied. Comparison device 15, Which will be described in greater detail below, receives another 20-bit BCD signal in parallel form from position feedback transducer 17.

Transducer 17 may take the form of any appropriate device for producing a fluidic (or electronic, photoelectric, etc.) signal as a function of the position of the control device. A typical transducer for providing such a function may be found in U.S. Patent No. 3,239,142, issued Mar. 8, 1966 to G. A. Lavine. As indicated in said patent, the device or tool'which is being position-controlled may rotate (wherein the signals fed to the comparison device will be angular position information) or may move rectilinearly. In either case, the information fed from transducer 17 to comparison device 15 is in BCD form. Comparison device 15 compares the two signals as received from the reader 13 and the transducer 17 to produce an error signal representative of the diflerence between the two signals. For predetermined differences between said signals difierent discrete error signal levels are produced as will be described below to activate drive mechanism 19 at respectively different speeds. Drive mechanism 19 may be any appropriate motor to perform the function of positioning machine tool 21. As machine tool 21 is driven closer to the command position by motor 19, the signal received at comparison device 15 from transducer 17 approaches the value of the command signal received by comparison device 15 from block tape reader 13. Thus the error signal output from comparison device 15 be comes smaller in discrete steps as discrete predetermined differences between the command and position signals are effected. For example, if a four speed drive is desired, the tool may be driven at 1200 inches per minute for differences between the command and position signals above a predetermined value. In the range of signal diflerences below said predetermined value, but above a second predetermined value, a motor speed for driving the tool at 120 inches per minute can be eflected. In the range between said second predetermined value and a third predetermined value, the motor speed can be reduced to 12 inches per minute at a diflerence range between said third predetermined value and the diflerence equivalent to the positioning resolution of the system, the motor can be driven at 1.2 inches per minute. Once the diflerence between the command signal and the position signal reaches a value equivalent to the system resolution the motor will stop, since the tool has been positioned with the desired accuracy for purposes of this embodiment. As will be described in greater detail later, a positioning accuracy of one-one thousandth of an inch is required for this system as described. This should in no way be construed however as limiting the ranges of resolution for which the logic network of this invention can be utilized.

FIGURES 2a and 2b represent, respectively, a block and schematic representation of the basic circuit element used in the comparison device 15 of FIGURE 1.

As seen in FIGURE 2a, comparison element 0,, representative of any individual comparison stage, receives an input A; and B from the corresponding bit of the command word A at the block tape reader 13 and the position word B at the feedback transducer 17, respectively. Comparison unit C of which will be required if the A and B signals are each 20 bits long, produces four output signals: when A B when B A 0, when A =B,; and 5, when A B FIGURE 2b schematically illustrates the component parts of block C and the appropriate connections for the corresponding input and output signals. As indicated signals A, and B are fed to the two input passages 27 and 25, respectively, of fluid AND gate 23. AND gate 23 may be of the type disclosed in Fluid Logic Device and Circuits by A. E. Mitchell et al., published by The Society of Instrument Technology, February 1963, FIGURE 4(a), wherein input passages A and B and output Z-B, A-B, and A-F correspond respectively to input passages 27 and 25, and output passages 31, 33, and 29 of gate 23 herein.

For purposes of this description, a binary logic convention will be employed wherein binary one is represented by the presence of a fluid stream, and binary zero by the absence of a fluid stream. As indicated, when A, is 1 and B is 0 a output is present at output passage 29 of the AND gate. This is so because the fluid stream representative of the binary 1 for A is undeflected in the fluid AND gate and is thus free to proceed directly to output passage 29 which is positioned to receive such an undeflected fluid stream. Similarly, when E, is binary 1 and A is binary 0 the fluid stream present at input terminal 25 representative of B, being binary 1 produces a output at output passage 31. When both A, and B are binary 0 there is no fluid stream input at either of the input terminals of AND gate 23 and thus there can be no output stream at either of output passages 29 or 31. When both A and B are binary 1 there are equal pressure fluid streams at input passage 25 and input passage 27 which interact within the fluid AND gate to produce a resulting stream that is directed through vent passage 33. Thus, neither the nor output is energized in this condition. Inputs A, and B are also supplied to input passages 37 and 39, respectively of fluid EXCLUSIVE OR gate 35. Fluid EXCLUSIVE OR gate 35 may be of the type disclosed in the above-referenced Mitchell et al. publication, FIG. 4(b), wherein input passages A and B, and output passages A-B and A-F-i-Z-B correspond respectively to input passages 37 and 39 and output passages 47 and of gate 35 herein. When A, is binary 1 and B is binary 0 a fluid stream is applied to input passage 37 and is free to flow via passage 41 to output passage 45 of the EXCLUSIVE OR gate. When B is binary 1 and A, is binary 0 the fluid stream indicative of the binary 1 state of B is applied to input passage 39 of the EXCLUSIVE OR gate, and is permitted to flow through passage 43 to output passage 45. When both A and and B, are binary zero, there are no fluid input streams at passages 37 and 39 and therefore no fluid output is present at the EXCLUSIVE OR gate output passage 45. When both A, and B, are binary 1 fluid streams appear at both input passages 37 and 39 of EXCLUSIVE OR gate 35. These fluid streams being of equal pressure interact within the EXCLUSIVE OR gate to form a resultant stream which is directed to vent passage 47. Thus there is no fluid stream at output passage 45 unless A alone or B alone are present as binary 1 inputs to the EXCLUSIVE OR gate. The output stream from passage 45 of the EXCLUSIVE OR gate 35 is fed to the input passage of amplifier-inverter 49 which may be of the type disclosed in Fluidics, published in August 1965 by Fluid Amplifier Associates, Inc., Boston, Massachusetts, page 243, FIGURE 2 wherein control nozzle A, and output passage K and A correspond respectively to passage 45, an output passages 53 and 51 of amplifier-inverter 49 herein. The power stream which has no reference designation in the publication, is not illustrated in the schematic representation of amplifier-inverter 49' herein. A signal from output passage 45 of EXCLUSIVE OR gate 35 acts to deflect the power stream (not illustrated) applied to amplifierinverter 49 to output passage 51 so as to produce a 5 signal. Thus, any time A, or B,, but not both, are binary 1 there is a signal indicating such at output passage 51. In the absence of the fluid stream from output passage 45 to amplifier-inverter 49, the power stream is normally directed as a 0 signal to output passage 53 indicating that A and B are either both binary 0 or both binary 1 and hence both equal. Thus, it is seen that four output signals from the block C in FIGURE 2a can be simply and readily implemented using the three fluid logic elements, AND gate 23, EXCLUSIVE OR gate 35 and amplifier-inverter 49.

FIGURE 3 is a schematic representation of a complete stage of comparison and encoding device 15 of FIGURE 1, wherein the comparison circuit of FIGURE 2a and associated encoding logic are illustrated. The complete stage shown in FIGURE 3 is the general stage i for comparison and encoding device 15, and consequently the input and output signals described as associated with stage C in FIGURE 2a appear at the various input and output passages of this stage. The output signal is fed to input passage 57, of fluid NOR gate 55 This fluid NOR gate may be of the type illustrated in FIG- URE 1 of US. Patent 3,240,219 to E. M. Dexter and D. R. Jones, wherein control passage 57 and 58, of FIGURE 3 herein, and further wherein an additional control nozzle is provided as described in column 9, lines 30-34 to correspond to input passage 59, herein. In addition output passage 19 of FIGURE 1 of said patent corresponds to output passage 56, of NOR gate 55 of FIGURE 3 herein, and power nozzle 15 of FIG- URE 1 of said patent is not illustrated in the schematic representation of gate 55 herein. In addition, the output is fed to the C stage as an indication that B A where it serves a function which will subsequently be described. The output signal of comparison unit C is fed to input passage 67, of fluid NOR gate 66 NOR gate 66 is preferably of the same type as NOR gate 55 In addition, the output signal from comparison unit C is fed to the C stage where it too serves a function which will subsequently be described. The output of the C unit is fed to input passages 59 and 69, of fluid NOR gates 55, and 66 respectively. The 0 is fed to input passage 61, of fluid OR gate 60 Fluid OR gate 60 may be of the type described in FIGURE 1 of the aforementioned US. Patent 3,240,219 to E. M. Dexter and D. R. Jones wherein control nozzles 16 and 17 correspond to input passages 61, and 63, herein respectively and wherein output passage 20 corresponds to output passage 62, herein. The power nozzle of said patent is not illustrated in the schematic representation of OR gate 60 It is to be understood that additional control nozzles may be added to OR gates of this type in accordance with the description in column 9, lines 3034 of the Dexter et a1. patent. A 0 signal from stage C is applied to input passages 58, and 68 of fluid NOR gates 55 and 66 respectively, and is also applied to input passage 63, of OR gate 60 This signal indicates that a non-zero condition exists for some stage of higher order than C and is received directly at stage C, from an output passage 62 (not shown) of the stage C which corresponds to output passage 62 of OR gate 60 in stage C An output signal at NOR gate output passage 56, is passed to input passage 71, of fluid OR gate 70 In addition an output signal at NOR gate output passage 65, of fluid NOR gate 66 is presented as an input signal at input passage 75, of fluid OR gate 77 Fluid OR gate 70 and fluid OR gate 77 are preferably of the same type as fluid OR gate 60, described above. An additional input signal to fluid OR gate 70 is provided from the C stage to input passage 78, 'and is present when C is positive and C is negative An output signal from fluid OR gate 70, appears at output passage 73,. Similarly, fluid OR gate 77, receives an additional input signal at input passage 76,, this signal also being provided from the C stage and representing the condition that C is negative and C is positive The output signal from fluid OR gate 77, appears at output passage 74,. The output signals at output passages 73, and 74 are passed to the respective input passages 81, and 88 of respective conditional logic gates 80 and 85 Conditional logic gates 80', and 85 may be of the type described in FIGURE 1 of the aforementioned US. Patent No. 3,240,219 to E. M. Dexter and D. R. Jones, wherein power nozzle 15, control nozzle 16, output passage and output passage 21 correspond to input passages 81, and 82 and output passages 83; and 84 respectively. For this application of the Dexter et al. logic gate, control nozzle 17 is not employed and may be vented or sealed 01f as desired. Output passage 84, of fluid OR gate 80 is disposed to receive an undeflected fluid input stream at input passage 81,. Similarly, output passage 87, of fluid OR gate 85, is disposed to receive an undeflected fluid stream applied at input passage 88 An additional input signal from the C stage is applied to input passage 82, of conditional gate This signal is present when B A Input passage 82,- is disposed such that an input stream applied thereto deflects an input stream appearing at input passage 81, of conditional logic gate 80 to form a resultant output stream directed towards output passage 83,. The output stream at output passage 83, is fed to input passage 78, of the C stage, corresponding substantially to the input passage at 78, of OR gate 70 in the C, stage. In like manner an additional input signal is applied to conditional logic gate at input passage 86 This input signal emanates from stage C and is present when A B The fluid signal at input passage 86, is normally directed to deflect a fluid input stream appearing at input passage 88 to output passage 89, of conditional logic gate 85 The output signal from output passage 89, is applied to the C stage at an input passage 76 (not shown) of an OR gate 77 (not shown) so a to correspond to the input signal appearing at input terminal 76 of OR gate 77 in the C stage.

It is to be noted that output signal +A at output passage 84 and output signal B at output passage 87, represent the system output signals from the C, stage. That is, one of these signals will be present when the logic conditions, to be described in detail below, prescribe that the C stage determines the magnitude of the approximated error signal produced by comparison device and encoder 15 of FIGURE 1.

FIGURE 4 is schematic illustrating eight stages of comparison device and encoder unit 15. Only two decades (eight stages) are illustrated in order to simplify the description of the device, it being understood that the remaining three decades (twelve stages) or more if necessary in particular applications are similarly interconnected and operate identically. It is readily seen that each of the eight illustrated stages is substantially the same as stage C, illustrated in FIGURE 3. Where appropriate in the description that follows, reference numerals employed in FIGURE 3 are associated with similar elements in FIGURE 4, but include a numerical subscript representative of the particular stage with which the element belongs in place of the i subscript employed in FIGURE 3.

The first mode of operation to be described is concerned with Rules (1) and (2) outlined above and provides for the determination of the polarity and approximate magnitude of the difference between command signal A and position signal B when the highest order nonzero C stage is not immediately preceded by lower order stages of opposite polarity. Initially, the highest order non-zero C stage (C generates a signal which inhibits certain logic circuits associated with all of the lower order C stages. For example, if signals A and B at comparison stage C are not equal, the 0 output signal will be energized. This signal appears at input passage 61;; of OR gate 60 OR gate 60 produces an output when any of its input passages are energized, so that in our example an output signal appears at output passage 62 The signal from passage 62 is passed to stage 7 where it is applied at input passages 58- 68 and 63 of NOR gate 55 NOR gate 66 and OR gate 60 respectively. NOR gates operate so as to produce an output signal only when none of their input passages are energized. Thus, the signal from ouput passage 62 serves to inhibit both NOR gates 55, and 66 In addition the signal at output passage 62 activates OR gate 60 via input passage 63-; so as to produce a signal at output passage 62 The output signal at passage 62 is in turn passed to stage 6 where it is applied to input passages 58 and 68 of NOR gates 55 and 66 respectively, thereby in- 15 hibiting these NOR gates. In addition, the signal from passage 62-; is applied to input passage 63 of OR gate 60 to produce an output signal or OR gate output passage 62 The signal appearing at passage 62 may be traced further on through all lower order stages where it inhibits the NOR gates 55 and 66 and activates OR gates 60 of these stages in a manner identical to that described for stages 6 and 7. It is to be noted that OR gate 60 may be activated by an input signal at input passage 61 whenever Aq7 =B 1 so as to produce a 5 signal, and also that OR gate 60 may be activated by an input signal at input terminal 60 whenever A B to produce signal Since the same relationship holds true in every stage, i

it is clear that an inequality of input signals A and B, at any stage C, produces an output signal 0, which acts to inhibit the NOR gates 55 55 etc. 55 and 66, 66 etc. 66 associated with all stages of lower order than C,. Thus, a stage 8 inequality inhibits the NOR gates in stages 7 through 1, a stage 7 inequality inhibits the NOR gates in stages 6 through 1, etc. Therefore, only the highest order non-zero C stage will have a NOR gate (SS or 66 which is not inhibited. In view of this, therefore, if we assume in our illustrative example that A =binary 1, B =binary 0, the signal is produced and NOR gate 55 will be the only one of NOR gates 55, and 66 (all stages) to provide an output signal. This is so because all of these NOR gates in stages 7 through 1 are inhibited as described above, because NOR gate 66 is inhibited by the (A B signal applied at input passage 67 and because neither (B A nor the 1 s=B is present at input passages 57 and 59 respectively to inhibit NOR gate 55 Consequently an output signal is present at output passage 56,; of NOR gate 55 and is applied as an input signal to input passage 71 of OR gate 70 OR gate 70 is activated thereby to produce an output signal at output passage 73 which is in turn passed to input passage 81 of conditional logic gate 80 In the absence of a signal at input passage 82,; of this gate, which for purposes of this example we assume to be the case, the signal at passage 81 produces a signal at output passage 84 which in turn provides the +.080 output signal. The absence of a signal at input passage 82 of conditional logic gate 80 is based on the assumed condition that stage C is not of the opposite polarity to stage C and therefore the signal 7 is not produced by stage C System operation for conditions when this signal is present will be described in detail below. For purposes of this example, however, the +.080 signal is the only system output signal for the logic network. This may be better appreciated by considering the following conditions which exist Each of NOR gates 66 through 66 are inhibited as described above, thereby precluding input signals to OR gates 77 through 77 via these NOR gates. In addition, since OR gate 77 has only one input passage, and since this passage is not energized by a signal, OR gate 77 produces no output signal, and consequently provides no input signal at input passage 85 of the conditional logic gate 88 With no input signal at input passage 85 there can never be an output signal at either of output passages 87 and 89 of conditional logic gate 88 The absence of an output signal at output passage 87 precludes the existence of -.080 system output signal. Further, the absence of an output signal at output passage 89 prevents energization of input passage 76 of OR gate 77 As input passage 757 of OR gate 77 is similarly unenergized, there is no signal at output passage 74, of OR gate 77 Thus, there can be no input signal to input passage 85; of conditional logic gate 88 and consequently neither output passage 87 89 of gate 88 is energized. Absence of a signal at passage 87; precludes the presence of the 0.040 system output signal, and absence of a signal at passage 89; operates to preclude output signals at stages 1 through 6 in a manner sim ar to that in which the absence of a signal at passage 89 has been illustrated to preclude the presence of the .040 signal. Similarly, the presence of system output signals +001 through +.040 is pre eluded so long as the 7(B7 A7) signal is not produced at stage 7 (C is not of opposite polarity to C Thus OR gates 70 through 70 receive no input signals from their associated inhibited NOR gates 55 through 55-; respectively or from the output passage 83 of the next higher order stages.

Since for A B +.080 is the energized system output signal for the example described above, the approximated error, as obtained from A in Table l, is +00.080, irrespective of the states of stages C through C and provided C is not in the state (B A The next mode of operation to be described concerns Rule 3 outlined above and provides for the correction of the error signal whenever the highest order non-zero C stage (C is of a different polarity than one or more of the immediately preceding lower order C stages. For purposes of this description, assume Ag=binary 1, B =binary O as above. Considering NOR gate 55 in stage 8 it i seen that the input signals at passages 57,; and 59 and 0 respectively, are not present and therefore NOR gate 55 produces signal at output passage 56 On the other hand, the only output signal from unit C is which indicates that A is greater than B The signal at output passage 56 activates OR gate 70 to produce a signal at input passage 81 of conditional logic gate in the manner described above. If we assume now that stage C (C is of opposite polarity to stage C (C then BI7 A7 and the signal is supplied by stage C; to input passage 82 of gate 80 Such a signal deflects the fluid signal from input passage 81 towards output passage 83 removing the output signal from passage 84 Thus the change in polarity from stage C (C to C (C results in a signal which inhibits the +080 signal even though A B We may now define the logic conditions for output passages 84 and 83 of conditional logic gate 80 as follows:

(a) There is no output at either of passages 84 or 83 when A is not greater than B (b) If A B and B is not greater than A, there is a +.O80 output signal at passage 84,; indicating that the magnitude of signal C is the magnitude of A unconditionally (following Rule 2).

(c) If A B andB A then no output signal exists at passage 84 and A does not control the magnitude of signal C. Rather, A conditionally controls the magnitude of signal C and this i indicated by the signal present at 83 (following Rule 3).

The output signal at output passage 83 is fed to stage 7 at input passage 78 of OR gate 70 to produce an output signal at output passage 73-; which is applied to input passage 81 of conditional logic gate 80,, thereby priming conditional logic gate 80 to produce a +.040 system output signal at passage 84 as long as no input signal is receive-d from C at passage 82 As was explained above for input terminal 82 of conditional logic gate 80 there is an input signal to passage 82 only when the B input signal to the next lower order stage C is greater than the A input signal to that stage. When the signal is present there is no output sig nal at passage 84 but rather there is an output signal I at output passage 83 such signal being fed to OR gate 70 to in turn provide an input signal at input passage 81 of conditional logic gate 80 Thus, a change in polarity between C (the highest order non-zero C bit stage and C,,, removes magnitude determination controlfrom C and places such control in C or some lower order stage if the polarity of C persists in said lower order stages. This overall operation may be best understood by referring to a specific example.

From Rule 3 of our general rules promulgated above it is apparent that the magnitude of the C error signal should the controlled by stage 6 while the polarity should be determined by stage 8 and is in the A (or direction. Checking our circuit to see that this is in fact implemented, we see that the signal appearing at input passage 67 inhibits NOR gate 66 The output signal of stage C is not present and the output signal of C is not present, therefore NOR gate 55 is not inhibited and a signal exists at output passage 56 This signal activates OR gate 70 which in turn provides a signal to input terminal 81 of conditional logic gate 80 In addition, the 0 output of stage C is applied to OR gate 60 to produce an output signal at passage 62 As described above, this signal, in conjunction with the various OR gates 60 in stages 2-8, operates to inhibit NOR gates 55 and 56 in each of the stages 1-7. Stage 7 inputs A7 and B are such that B A according to our hypothesis. Thus while the output signals of stage C are blocked by inhibited NOR gates 55, and 66 the output signal from stage C; appears at input terminal 82 of conditional logic gate 80 in stage C The fluid input stream at input 81 is deflected thereby to output passage 83 and appears at passage 78 of OR gate 70 in stage 7. The OR gate output signal appears as an input signal at input passage 81; of conditional logic gate 80 Since B is greater than A there is also a signal generated from stage C which appears at input passage 82 of the stage 7 conditional logic gate 80 This signal acts to deflect the fluid stream input at input passage 81 towards output passage 83 The output signal from passage 83 is applied at input passage 78 of OR gate 70 in stage 6. OR gate 70 is thus activated to produce a signal at input passage 81 of conditional logic gate 80 Under our hypOthesis A =B and therefore the output signal of unit C is not energized and no input signal appears at input terminal 82 of conditional logic gate 80 Thus the fluid signal appearing at input terminal 81 is free to pass to output passage 84 thereby providing a +.020 system output signal which determines the magnitude and polarity of the approximate error signal.

In order to demonstrate how the system of FIGURE 4 conforms to the requirements of Rule 4 when one of C C etc. is the highest order stage in a decade, Example 8 is presented.

EXAMPLE 8 These conditions bring us to a point similar to that existing under the above described Example 7 wherein a signal appears at input passage 81 of conditional logic gate 80 However, in the present example, since B A signal is generated at stage C and appears at input terminal 82 of stage 6 to deflect the fluid stream appearing at passage 81 from passage 84 towards output passage 83 thereby removing the +020 system output signal from output passage 84 The signal at output passage 83 is applied to OR gate 70 in stage 5 at input passage 78 Thus energized, OR gate 70 produces a signal at output passage 73 which is applied to input passage 81 of conditional logic gate 80 Since according to our given conditions B A a., signal is produced by stage C and is applied to 82 of conditional logic gate 80 to deflect the signal present at input passage 81 towards output passage 83 It is to be noted that stage C; is the highest order stage in the decade determined by stages C through (3.; and that stage C would have been the stage determining the magnitude of the error signal (+010 system output signal) had there been no signal generated at stage C Thus, the chain of stages C C etc. which immediately precede the highest order nonzero stage C (C and are opposite in polarity thereto, include the highest order stage (C of a decade (decade 1). According to Rule 4 promulgated above, such a condition should result in a shift to the second (C or third (C highest order stage of that decade depending on the state of these stages. First let us assume that both C and C are 0 (A =B A =B Under these conditions, the signal at output passage 83 is connected to input passage 101 of OR-NOR gate 100.

OR-NOR gate 100 may be of the type illustrated in FIGURE 1 of US. Patent 3,240,219 to E. M. Dexter and D. R. Jones, wherein power nozzle 15, control nozzles 16 and 17, and output passages 19 and 20 correspond respectively to input passages 101, 102, and 103 and output passages 104 and 105 of gate 100. This gate operates such that a signal at input passage 101 appears at output passage 104 when neither of input passage 102 and 103 has a signal applied thereto. If a signal is applied to either of passages 102 or 103, the signal from input passage 101 is deflected towards output passage 105. Input passage 102 is connected to receive a signal from stage C and input passage 103 is connected to receive a signal from stage C Since we have assumed A =B and A =B neither of the or signals is present and the input signal at input passage 101 is permitted to pass undeflected to output passage 104 of OR-NOR gate 100. In accordance with Rule 4(a), the output signal from passage 104 is applied to stage C to OR gate 70 at input passage 72 to activate said gate and produce an output signal at output passage 73 This signal is in turn passed to input passage 81 of conditional logic gate Operation then continues as described above as though stage C were a part of the unbroken chain of stages C C etc. having opposite polarity to C,,,. Thus, if a signal is produced at stage C (B A the signal at passage 81 is deflected towards output passage 83 which in turn activates OR gate 70 to produce a +.00l system output signal thereby making stage C the magnitude determinative stage. On the other hand, if the signal is not present, the signal at passage 81 is not deflected and a +.002 system output signal from stage C results.

If, in the above example, instead of having 0 :0 and C =0 there had been a signal produced at one or both of these stages, slightly different results would have ensued. This will be explained by assuming that stage C produce a signal (A B and describing system op eration therefor. Initially it must be pointed out that if a signal is produced by stage C (B A neither C nor C can be in the state since either condition would call for the first decade of the B signal (stages B through B to have a value greater than decimal 9. Thus, when C is C and C can only be in the or 0 states. Returning to our example, if C produces a signal (A B a signal appears at input passage 103 of OR- NOR gate and deflects the signal at input passage 101 to remove the signal from passage 104 and to produce an output signal at output passage 105. (The same result would have ensued if C were in the state, the deflecting signal, appearing at passage 102; and similarly the same result would ensue if both C and C were in the state, the deflecting signals and appear ing respectively at passages 102 and 103.) The output signal at passage 105 is applied to input passage 79 of OR gate 70 in stage C in accordance with the requirements of Rule 4(b). This serves to activate OR gate 70 producing an output signal at output passage 73;, which is applied to input passage 81 of conditional logic gate 80 As explained above, under the conditions assumed for this example wherein stage C; is the signal can never be produced at stage C and consequently there can never be a signal at passage 82 to deflect the signal appearing at passage 81 Thus, as required by Rule 4(b), the system output signal is +.004. The operation described in the preceeding examples in which the polarity of the highest order non-zero C stage was positive follows in identical fashion when the highest order non-zero C stage is negative. This is true because all of the circuitry on the left side of FIGURE 4 has identical counterparts 19 on the right side of the figure, and the counterpart circuitry takes control over system operation for a negative error signal. Therefore, to avoid repetition, operation of the system for a negative difference between A and B will not be described.

The next mode of operation to be described concerns the condition when the command signal A and the position signal B are equal. It is to be noted from FIGURE 3 that the output signal of stage C, acts to inhibit NOR gates 55, and 66 Thus, when all of the bits in the B signal become equal to respective bits in the A signal, all of the C stages will produce 0 output signals which inhibit respective associated NOR gates 55 and 66, thereby preventing generation of any of the system output signals +.001 through +.0 80 and .001 through .008. Another result of all of the B bits becoming equal to all of the A bits is that none of the U signals are generated in any of the stages. Thus, none of the OR gates 60;, through 60 are activated and the NOR gate 110 associated with stage C receives no input signal. NOR gate 110 is preferably identical to NOR gates 55 'and 66,. With no input signals applied to inhibit NOR gate 110, a STOP output signal appears at passage 111 to stop the drive mechanism or motor 19 of FIGURE 1.

It is to be understood that while FIGURE 4 and the detailed operational description therefor'relate to a twodecade, eight stage system, the operation of a three, four, five or more decade system is substantially the same. The interconnections within each decade for larger systems are identical to those shown in FIGURE 4. Connections between decades for larger systems are substantially the same as shown in FIGURE 4, it being understood that OR-NOR gate 100, illustrated as associated with the first decade, is required for all decades except the highest order decade.

The standard comparison unit of FIGURES 2a and 2b and utilized as element C in FIGURE 4 may be comprised of the Digital Comparator device disclosed in my co-pending application Ser. No. 499,782, entitled Digital Comparator, filed Oct. 21, 1965, and assigned to the same assignee as the instant invention.

FIGURE 5 schematically illustrates one possible manner of employing the system output signals generated in the system of FIGURE 4 to provide discrete ranges of speed control for drive mechanism 19 of FIGURE 1. Comparison block 120 represents the system of FIGURE 4 with the various system output signals (+.O01 through +.080 and .001 through .080) grouped arbitrarily as input signals to various OR gates 121 through 126. It is to be understood that the particular signal grouping illustrated in FIGURE 5 is meant to be representative only, and that any grouping or number of groups may be employed insofar as they define meaningful error signal ranges. For example, one would not group the +.002 signal with the -|-.040 and +1180 signal, etc. Thus, as illustrated, signals +.080 and +.040 are the input signals for OR gate 121, signals +.020, +1010, and +.008 are the input signals for OR gate 122, signals +.OO4, +.0(l2, and +.001 are the input signals for OR gate 123, signals .080, and -.040 are the input signals for OR gate 124, signals .0.20, .010, and .008 are the input signals for OR gate 125 and signals .0O4, .O02 and .001 are the input signals for OR gate 126. OR gates 121 through 126 are preferably of the same type as OR gate 60 of FIGURE 3. The output signals from the OR gates 121-126 are connected to respective speed control devices 127 through 132 which in turn provide signals to drive mechanism 19. In addition, the STOP signal produced by NOR gate 110 of FIGURE 4 is connected to a stop control device 133, which in turn provides a signal to drive mechanism 19. The nature of control devices 127 through 132 depends on the nature of drive mechanism 19. For example, if drive mechanism 19' is a motor which operates at various speeds in either direction as a function of magnitude and polarity of electrical signals, control devices 127 through 132 may be fluid to electrical transducers. Or, if drive mechanism 19 is fluid operated, the control devices may be fluid amplifiers. In any case, control devices 127 through 132 must be capable of producing different signals which are recognizable at the drive mechanism as commands to I operate at different speeds and directions as necessary. Thus, if comparison block provides an approximate error signal +.08O or +.040, OR gate 121 is activated and in turn activates high speed control device 127. Control device 127 produces a signal which commands high speed operation of drive mechanism 19 in the direction. In like manner, the various other output signals energize their associated OR gates and speed control devices such that the drive mechanism operates at high, medium, or low speed in either the or direction as a function of the approximate error output signal from comparison block 120.

Whenever the STOP output signal is energized, stop control device 133 is activated to produce a signal which provides a braking function at drive mechanism 19. As is the case for control devices 127 through 132, the nature of control device 133 depends on the nature of drive mechanism 19. All that is required of control device 133 is that it produce a signal which is recognizable at the drive mechanism as a braking command.

What has been described above is merely one of the many possible embodiments of the novel concepts of this invention. Further, the utilization of fluid circuitry in the above described embodiments should not be construed as limiting, since clearly the various logic elements of FIGURES 2, 3, 4 and 5 are well known in electronics and other fields.

While I have described and illustrated one specific embodiment of my invention, it will be clear that variation of the details of construction which are specifically illustrated and described may be resorted to without departing from the true spirit and scope of the invention.

I claim:

1. A logic nework for approximating the difference between two digital signals, each signal having a plurality of binary digits and each signal employing the same binary-type code, said binary-type code being such that all digits in each signal are assigned different decimal equivalent weights, said network comprising:

a plurality of comparison means for simultaneously and individually comparing the binary states of respective pairs of digits of equal weight and for individually providing indications of non-zero differences between said pairs of digits of equal weights and indications of the polarity of said non-zero difference;

logic means connected to said comparison means for providing an indication of the polarity of the difference between said two digital signals in accordance with the polarity of the difference between the compared pair of digits having the highest weight and having a non-zero difference, said logic means additionally providing an indication of the approximate magnitude of the difference between said digital signals in accordance with the weight of the compared pair of digits having the highest weight and having a non-zero difference;

correction means connected to said logic means and comparison means for inhibiting said approximate magnitude indication and providing a modified approximate magnitude indication in accordance with the weight of said next lower weighted pair of digits only when the difference between the highest-weighted pair of digits having a non-zero difference is of one polarity and the difference between the next lower weighted pair of digits is of opposite polarity, said correction means additionally including means for providing a further modified approximate mag nitude indication in lace of said modified approxiw wherein said binary-type code is a binary coded decimal means for providing said corrected approximate magnitude indication in accordance with the weight of the third highest weighted pair of digits in said any decade only when the differences between either said third highest weighted pair of digits or between the second highest weighted pair of digits in said any decade are of the same polarity as the polarity of the difference between said highest weighted pair of digits having a non-zero difference; further means for providing said corrected approximate magnitude indication in accordance with the weight of said second highest weighted pair of digits in said any decade only when the difference between neither said third nor said second highest Weighted pairs of digits in said any decade is of the same polarity as the polarity of the difference between said highest weighted pair of digits having a non-zero difference; means for inhibiting the corrected approximate magnitude indication provided by said further means and for providing a different corrected approximate magnitude indication only when the lowest weighted pair digits in said any decade has said opposite difference polarity. 3. A logic network for comparing two digital signals A and B, each employing a binary-type code, said signals defined by the expressions and respectively wherein A and B represent any one of n binary stages in respective ones of signals A and B, and wherein the weight assigned to each stage in said signals increases for increasing the values of i, and wherein equal weights are assigned to corresponding A and B said network comprising:

n comparison means for making n individual comparisons between the binary states of A and B to produce a plurality of signals C for representing the expression C =A -B for each of said states wherein the weights assigned to A and B are assigned to C and its respective comparison means;

logic circuit means connected to said It comparison means for providing a signal C representing the 22 highest-weighted of the non-zero C signals at any instant of time; conditional logic means connected to said logic circuit means and comparison means for:

(1) providing a logic network output signal representative of the polarity and weight of signal C the C signal having the next lower weight than C is either zero or of the same polarity as C and (2) inhibiting the network output signal representative of the polarity and weight of signal C when signal C is of opposite polarity to sig nal C and providng a network output signal having the polarity of signal C and the weight of signal C where C represents the lowest-weighted C signal of a sequence of x consecutively lower weighted signals of C having said opposite polarity;

wherein said C signals produced at each comparison means comprise:

(a) a signal, indicating that A B (b) a signal, indicating that B A (c) a signal, 0 indicating that A =B and (d) a signal, 5 indicating that Aj$ B1;

and wherein said logic circuit means comprises:

n-1 OR gates associated respectively with all but the lowest weighted comparison means;

2n pairs of NOR gates, each pair associated with a respective one of said n comparison means;

means for connecting an output signal from each NOR gate to said conditional logic means;

means for connecting the 6 signal produced by all but lowest weighted comparison means an an input signal to the respective OR gate associated with that comparison means;

means for' providing an additional input signal to the OR gates associated with all but the highest order comparison means from the output signal of the OR gate associated with the respective next higher weighted comparison means;

means for connecting the output signals of each of said OR gates as input signals to both NOR gates of the pair associated with the respective next lower weighted comparison means to inhibit each pair of NOR gates associated with a comparison means having a lower weight than the highest weighted comparison means producing a 6 signal.

4. The logic network of claim 3 wherein said logic circuit means further comprises:

means for connecting the 0 signal produced by each comparison means as an input signal to both of the pair of NOR gates associated with that comparison means;

\nd means for connecting the signal produced by each comparison means as an input signal to a first of the pair of NOR gates associated with that comparison means, and for connecting the signal produced by each comparison means as an input sig nal to a second of the pair of NOR gates associated with that comparison means;

whereby no more than one of all of said NOR gates is permitted to provide an input signal to said conditional logic means at any instant of time, said one of all of said NOR gates being associated with the highest weighted comparison means producing a 6 signal.

5. The logic network of claim 4 wherein said conditional logic means comprises:

2n pairs of OR gates, each pair associated with a respective one of said 11 comparison means;

2 pairs of conditional logic gates, each pair associated with a respective one of the (rt-1) highest weighted comparison means, each of said conditional logic gates having a first and second input means and a first and second output means, said first output means providing a first output signal only when an input signal is applied to said first input means and no signal is applied to said second input means, and said second output means providing a second output signal only when input signals are applied to both of said first and second input means;

means for connecting an output signal from the first of each of said pairs of NOR gates as an input signal to a first of the pair of OR gates associated with the same comparison means;

means for connecting an output signal from the second of each of said pairs of NOR gates to a second of the pair of OR gates associated with the same comparison means;

means for connecting an output signal from the first of the (11-1) highest weighted of said pairs of OR gates as an input signal to the first input means of the first of the pair of conditional logic gates associated with the same comparison means;

means for connecting an output signal from the second of the (n1) highest weighted of said pairs of OR gates as an input signal to the first input means of the second of the pair of conditional logic gates associated with the same comparison means;

means for connecting the signal produced by the (n-l) lowest weighted comparison means as an input signal to the second input means of the first of the pair of conditioned logic gates associated with the respective next higher weighted comparison means;

means for connecting the signal produced by the (11-1) lowest weighted comparison means as an input signal to the second input means of the second of the pair of conditional logic gates associated with the respective next higher weighted comparison means;

and means for connecting each of the second output means of all of said conditional logic gates to provide network output signals.

6. The network of claim 5 wherein said conditional logic means further comprises:

means for connecting an output signal from said second output means of the first of each of said pairs of conditional logic gates as an input signal to the first of the pair of OR gates associated with the next lower weighted comparison means;

means for connecting an output signal from said second output means of the 'second of each of said pairs of conditional logic gates as an input signal to the second of the pair of OR gates associated with the next lower weighted comparison means.

7. The network of claim 5 wherein said binary-type code is a binary-coded-decimal code having four digits representating each decade and wherein n has a value of at least eight, said conditional logic means further comprising:

a pair of OR-NOR gates associated with all but the highest order decade, each of said OR-NOR gates comprising first, second, and third input means and first input means for providing an output signal only when an input signal is present at said first input means and no input signals are present at either of said second and third input means, and a second output means for providing an output signal only when an input signal is present at said first input means and an input signal is present at at least one of said second and third input means;

means for connecting an output signal from the second output means of the first of each of those pairs of conditional logic gates which are associated with the second, third and fourth highest Weighted comparison means of each decade as an input signal to the first of each of the pair of OR gates associated with the next lower weighted comparison means;

means for connecting an output signal from the second output means of the second of each of those pairs of conditional logic gates which are associated with the second, third and fourth highest weighted comparison means of each decade as an input signal to the second of each of the pair of OR gates associated with the next lower weighted comparison means;

means for connecting an output signal from the second output means of the first of each pair of conditional logic gate which is associated with the lowest weighted comparison means in all decades except the lowest order decade as an input signal to the first input means of the first of the pair of OR-NOR gates associated with the next lower order decade;

means for connecting an output signal from the second output means of the second of each pair of conditional logic gates which is associated the lowest weighted comparison means in all decades except the lowest order decade as an input signal to the first input means of the second of the pair of OR- NOR gates associated with the next lower order decade;

means for connecting the signal produced by the third highest weighted comparison means of each respective decade except the highest order decade as an input signal to the second input means of the first of the pair of OR-NOR gates associated with the same respective decade;

means for connecting the signal produced by the third highest weighted comparison means of each respective decade except the highest order decade as an input signal to the second input means of the second of the pair of OR-NOR gates associated with the same respective decade;

means for connecting the signal produced by the second highest weighted comparison means of each respective decade except the highest decade as an input signal to the third input means of the first of the pair of OR-NOR gates associated with the same respective decade;

means for connecting the signal produced by the second highest weighted comparison means of each respective decade except the highest decade as an input signal to the third input means of the second of the pair of OR-NOR gates associated with the same respective decade;

means for connecting a signal provided at the first output means of the first of each pair of OR-NOR gates as in input signal to the first of the pair of OR gates associated with the second lowest weighted comparison means in the decade with which the respective OR-NOR gate is associated;

means for connecting a signal provided at the first output means of the second of each pair or OR- NOR gates as an input signal to the second of the pair of OR gates associated with the second lowest weighted comparison means in the decade with which the respective OR-NOR gate is associated;

means for connecting a signal provided at the second output means of the first of each pair of OR-NOR gates as an input signal to the first of the pair of OR gates associated with the second highest weighted comparison means in the decade with which the respective OR-NOR is associated;

means for connecting a signal provided at the second output means of the second of each pair of OR-NOR gates as an input signal to the second of the pair of OR gates associated with the second highest weighted comparison means in the decade with which the respective OR-NOR gate is associated.

8. The network of claim 7 wherein each of said 12 comparison means comprises:

logic gate means having first and second input means and first and second output means for providing a first output signal at said first output means only when an input signal is present at said first input means and no signal is present at said second input means and for providing a second output signal at said second output means only when an input signal is present at said second input means and no signal is present at said first input means;

EXCLUSIVE OR gate means having first and second input means and an output means for providing an output signal when onlp one of said first and second input means receives an input signal;

means for connecting a signal representative of the binary state of A, to the first input means of both said logic gate means and said EXCLUSIVE OR gate means;

means for connecting a signal representative of the binary state of B, to the second input means of both said logic gate means and said EXCLUSIVE OR gate means;

amplifier-inverter means comprising one input means, a first output means for providing a first output signal only when a signal is present at said one input means, and a second output means for providing a second output signal only when no signal is present at said one input means;

means for connecting the output means of said EX- CLUSIVE OR gate means to the one input means of said amplifier-inverter means;

whereby, the first output means of said logic gate means provides the signal, the second output means of said logic gate means provides the signal, the first output means of said amplifierinverter provides the (T signal, and the second output means of said amplifier-inverter means provides the signal.

9. The network of claim 8 wherein digital signal A represents a command position with respect to an arbitrary zero position of a device which is to be positioncontrolled, and wherein digital signal B represents the actual position of said device, said network further comprising:

a variable speed drive mechanism for controlling the position of said device;

signal conversion means connected to the first output means of all of said conditional logic gates and connected to said drive mechanism for driving said drive mechanism at a plurality of diflerent speeds in accordance with the presence of a signal at predetermined ones of said first output means of said conditional logic gates;

whereby said device is automatically positoned in accordance with said command position.

10. The combination of claim 9 wherein said device to be position-controlled is a machine tool.

11. The combination of claim 10 wherein said two digital signals are fluid signals and wherein said comparison means, said logic circuit means, said conditional logic means, and said OR-NOR gates comprise pure fluid elements.

12. The network of claim wherein each of said It comparison means comprises:

logic gate means having first and second input means and first and second output means for providing a first output signal at said first output means only when an input signal is present at said first input means and no signal is present at said second input means and for providing a second output signal at said second output means only when an input signal is present at said second input means and no signal is present at said first input means;

EXCLUSIVELY OR gate means having first and second input means and an output means for providing an output signal when only one of said first and second input means receives an input signal;

means for connecting a signal representative of the binary state of A to the first input means of both said logic gate means and said EXCLUSIVE OR gate means; 7,

means for connecting a signal representative of the binary state of B, to the second input means of both said logic gate means and said EXCLUSIVE OR gate means;

amplifier-inverter means comprising one input means,

a first output means for providing a first output signal only when a signal is present at said one input means, and a second output means for providing a second output signal only when no signal is present at said one input means;

means for connecting the output means of said EX- CLUSIVE OR gate means to the one input means of said amplifier-inverter means;

whereby, the first output means of said logic gate means provides the signal, the second output means of said logic gate means provides the signal, the first output means of said amplifier-inverter provides the I), signal, and the second output means of said amplifier-inverter means provides the 0 signal 13. The network of claim 12 wherein digital signal A represents a command position with respect to an arbitrary zero position of a device which is to be positioncontrolled, and wherein digital signal B represents the actual position of said device, said network further comprising:

a variable speed drive mechanism for controlling the position device;

signal conversion means connected to the first output means of all of said conditional logic gates and connected to said drive mechanism for driving said drive mechanism at a plurality of different speeds in accordance with the presence of a signal at predetermined ones of said first output means of said conditional logic gates;

whereby said device is automatically positioned in accordance with said command position.

14. The combination of claim 13 wherein said device to be position-controlled is a machine tool.

15. The combination of claim 14 wherein said two digital signals are fluid signals and wherein said comparison means, said logic circuit means and said conditional logic means comprise pure fluid elements.

16. The combination of claim 13 wherein said signal conversion means comprises:

a plurality of output OR gates each having connected thereto a diflerent plurality of said first output means of said conditional logic gates;

a plurality of control means, each connected to receive an output signal from a different one of said output OR gates, and each responsive to a respective output OR gate signal to provide a diflerent level signal;

means connecting the different level signal from each of said control means to said drive mechanism for driving said drive mechanism at a direction and speed determined by signals present at the first output means of said conditional logic gates.

17. A position control system for positioning a device in accordance with a command signal, said command signal having a binary format comprising a plurality of increasingly weighted bits, said system comprising:

variable speed drive means responsive to individual ones of a plurality of input signals for moving said device at a corresponding plurality of individual velocities;

transducer means for providing a position signal representing the actual position of said device, said position signal having the same binary format as said command signal wherein each bit in said command signal has a corresponding equally Weighted bit in said position signal; comparison means for simultaneously and individually comparing the binary states of equally weighted bits in said command and position signals and for providing individual indications of non-zero differences between said equally weighted bits and indications of the polarity of said non-Zero differences;

logic means responsive to said comparison means for providing an indication of the polarity of the difference between said command and position signals in accordance with the polarity of the difference between the equally Weighted bits having the highest weight and a non-zero difference, said logic means additionally providing an indication of the approxitmate magnitude of the difference between said command and position signals in accordance with the weight of the equally weighted bits having the highest Weight and a nonzero difference;

correction means responsive to said logic means and comparison means for inhibiting said approximate magnitude indication and providing a modified approximate magnitude indication only when the difference between the highest-weighted pair of equally weighted bits having a non-Zero difference is of one polarity and the difference between the next lower weighted pair of equally weighted bits is of opposite polarity; and

control means responsive to said approximate magnitude indication and said modified approximate magnitude indication for applying said plurality of input signals to said variable speed drive means, said plurality of input signals being accorded respective weights representing respective ranges of differences between said command and position signals.

18. The system of claim 17 wherein said correction means comprises means for providing said modified approximate magnitude indication in accordance with the weight of the said next lower weighted pair of equally weighted bits.

19. The system of claim 18 wherein said correction means includes means for providing a further modified approximate magnitude indication in place of said modified approximate magnitude indication only when additional consecutively weighted pairs of equally weighted bits having weights immediately lower than said next lower weighted pair have differences of said opposite polarity, said further modified approximate magnitude indication being provided in accordance with the weight of the lowest weighted pair, one of said additional consecutively weighted pairs of equally weighted bits having said opposite difference polarity, and wherein said control means is additionally responsive to said further modified approximate magnitude indication.

20. The system of claim 19 wherein said binary format is a binary coded decimal code, wherein said command and position signals comprise at least eight bits each so as to represent the equivalent of at least two decades, said system further comprising:

additional correction means for inhibiting said further modified approximate magnitude indication and for providing in its place a corrected approximate magnitude indication only when one of a group of pairs of equally weighted bits comprising said next lower weighted pair and said additional consecutively weighted pairs include the highest Weighted pair in any decade.

21. A position control system for positioning a device in accordance with a command signal A, said command signal having a bianry format defined by the following expression where A, represents any one of n binary bits in command signal A, wherein the weight accorded each bit in signal A increases for increasing values of i, said system comprising:

variable speed drive means responsive to individual ones of a plurality of input signals for moving said device at a corresponding plurality of individual velocities; transducer means for providing a position signal B representing the actual position of said device, said position signal having the same binary format as said command signal A and defined by where B, represents any one of n binary bits in position signal B, and wherein equal weights are accorded corresponding A and B bits;

n comparison means for making It individual comparisons between the binary states of A, and B to produce a plurality of signals C representing the expression C =A B for each of said states wherein the weights assigned to A, and B are assigned to C and its respective comparison means;

logic circuit means connected to said It comparison means for providing a signal C representing the highest-weighted of the non-zero C signals;

conditional logic means responsive to said logic circuit means and comparison means for:

(a) providing a first logic signal representative of the polarity and weight of signal C when signal C the C signal having the next lower weight than C is either zero or of the same porality as C and (b) inhibiting said first logic signal when signal C is of opposite polarity to signal C and providing a second logic signal having the polarity of signal C and the weight of signal C where C represents the lowestweighted C signal of a sequence of x consecutively lower weighted signals of C having said opposite polarity; and

control means responsive to said first and second logic signals for applying said plurality of input signals to said variable speed drive means, said plurality of input signals being accorded respective weights representing respective ranges of difference between command signal A and position signal B.

22. The system of claim 21 wherein said C; signals produced at each comparison means comprise:

(a) a signal, indicating that A B (b) a signal, indicating that B A (c) a signal, 0,, indicating that A =B and (d) a signal, 6], indicating that A Bg and wherein said logic circuit means comprises:

n-1 OR gates associated respectively with all but the lowest weighted comparison means;

2n pairs of NOR gates, each pair associated with a respective one of said n comparison means;

means for connecting an output signal from each NOR gate to said conditional logic means;

means for connecting the 6 signal produced by all but the lowest weighted comparison means as an input signal to the respective OR gate associated with that comparison means;

means for providing an additional input signal to the OR gates associated with all but the highest order comparison means from the output signal of the OR 29 3O gate associated with the respective next higher References Cited weighted comparison means; means for connecting the output signals of each of said UNITED STATES PATENTS OR gates as input signals to both NOR gates of the 2,923,476 2/1960 Ketchledge 235177 pair associated with the respective next lower 5 weighted comparison means to inhibit each pair of EUGENE BOTZ, Plimary Examiner NOR gates associated with a comparison means having a lower weight than the highest weighted comparison means producing a 0 signal. 9013; 23515 1.1 1; 318-20 

